PoP is an integrated circuit (IC) packaging technique that allows vertically stacking of IC packages, such as a discrete logic ball grid array (BGA) package and a memory BGA package. Two or more packages are installed on top of one another, i.e. vertically stacked, with a standard interface to route signals between them. This allows higher density, for example for mobile telephone/PDA market applications.
Through substrate via (TSV)-containing IC die such as microprocessors TSV die in a PoP flow are generally not yet in production. However, the assembly flow for a conventional PoP sequence for a wafer having a plurality of TSV die (a “TSV wafer”) can be expected to be as follows:
1. Wafer probe (“multiprobe”) the respective die on a thick TSV wafer (e.g., 600 to 800 μm thick) having embedded TSVs to identify good die on the basis of electrical tests. Electronic Inking where the die are tracked on stored wafer maps may be used for subsequent identification of “bad” die.2. Singulate the TSV wafer to provide a plurality of singulated “good” TSV die.3. Die attach the good TSV die identified at wafer probe active circuit side down to a multi-layer (ML) package substrate that includes BGA pads on its bottom side that is typically attached to a carrier (typically a silicon or glass carrier) to form a PoP precursor. The carrier provides rigidity.4. Expose the embedded TSVs by thinning the bottom side of the TSV die (e.g. to about 30 to 100 μm) to form a thinned PoP precursor having contactable TSV tips. The active circuit side (i.e. frontside) of the TSV die is not electrically accessible via the package substrate due to the presence of the carrier.5. Ship the thinned PoP precursor to a customer.6. The customer (or its contactor) then (i) adds one or more die, such as a memory die, on top of the TSV die to make contact with the TSV tips or contact pads coupled to the TSV tips to form the PoP, and then (ii) the customer (or its contactor) removes the carrier and adds a BGA on the BGA pads of the package substrate.
Steps 3 and 4 in the above-described flow can result in electrical problems including TSV formation problems (e.g., missing TSVs), TSV contact problems (e.g., high resistance contacts) or shorts (e.g., TSV shorts to ground) that can only be detected after assembly of the top die to complete the PoP because as noted above the carrier while present blocks access to one side of the TSV die. The package substrate can also be the source of certain problems. Probing after die attach of the TSV die can be omitted. However, this will result in shipping some fraction of bad thinned PoP precursors onto step 6 described above for customer's assembly (e.g., where costly pre-packaged memory stacks may be added), that due electrical problems such as those described above that can result in failures at final PoP testing. There are no known practical solutions. What is needed is a method to test thinned PoP precursors to allow testing of the TSV die and one or more test parameters (e.g., including test parameters associated with the die attach process) of the TSV die from the same side (e.g., the topside), whether simply being more convenient or being necessary due to the presence of a carrier.